Freescale Semiconductor /MKL27Z4 /SIM /SCGC5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)LPTMR 0 (0)PORTA 0 (0)PORTB 0 (0)PORTC 0 (0)PORTD 0 (0)PORTE 0 (0)LPUART0 0 (0)LPUART1 0 (0)FLEXIO

PORTC=0, PORTE=0, PORTD=0, LPUART1=0, FLEXIO=0, PORTA=0, LPTMR=0, LPUART0=0, PORTB=0

Description

System Clock Gating Control Register 5

Fields

LPTMR

Low Power Timer Access Control

0 (0): Access disabled

1 (1): Access enabled

PORTA

Port A Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTB

Port B Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTC

Port C Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTD

Port D Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTE

Port E Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

LPUART0

LPUART0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

LPUART1

LPUART1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

FLEXIO

FlexIO Module

0 (0): Clock disabled

1 (1): Clock enabled

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